Huawei Challenges TSMC with "τ Scaling Law" Aiming for Equivalent 1.4nm Chips by 2031
Original: 挑戰台積電製程霸權？華為稱 2031 年實現等效 1.4 奈米晶片，提出「τ 縮放定律」
Huawei proposed the "τ scaling law" to achieve equivalent 1.4nm chip density by 2031 through design-side signal delay optimization.
To bypass US semiconductor equipment sanctions, Huawei has introduced the "τ (Tau) scaling law." Instead of physical transistor shrinking, this approach focuses on reducing signal propagation delay via design-level innovations like logic folding. Huawei aims to achieve performance equivalent to a 1.4nm node by 2031, challenging TSMC's lithography-centric dominance.
Facing the strict semiconductor equipment and technology blockades imposed by the United States in recent years, Chinese tech giant Huawei has published a brand-new "τ (Tau) Scaling Law," attempting to forge a different path from the chip design end and break the traditional physical process technology route dominated by wafer foundry leaders such as TSMC. Huawei claims that through this new law and design architecture, it aims to achieve the chip density and performance equivalent to 1.4-nanometer (equivalent 1.4nm) by 2031.
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